The present invention relates to integrated digital systems, and in particular, to a circuit for generating a clock signal from a frequency stable reference signal. More specifically, the invention relates to a phase-locked loop (PLL) for generating a clock signal at a frequency that is generally higher than the reference frequency.
Phase-locked loops (PLL) are increasingly used in digital systems integrated on silicon for generating a clock signal. Starting from a stable external reference signal generated by a quartz crystal or a ceramic resonator) having a relatively low frequency, the PLL provides to the integrated system a highly stable clock signal, at a frequency higher than that of the reference signal. Very often the frequency value may be readily programmed. From the same reference it is possible to obtain different clock frequencies simply by reprogramming the characteristics of the loop.
The use of a PLL for generating a synchronization signal and/or a relatively high frequency clock signal allows a reduction of electromagnetic emissions at the system level. This results in a savings of additional components used for filtering or noise suppression.
In electronic applications, particularly when exposed to high noises levels and in which the stability of the timing signal is fundamental for the functioning of digital electronic circuits, the control of the state of the phase-locked loop is very important. The output signal of the PLL is considered locked to the reference signal when the ratio between the respective frequencies (the reference input signal and the output signal from the PLL) is kept constant.
Stability is ensured by the architecture of the phase-locked loop, which implements a negative feedback loop used for detecting any temporary shift of the frequency of the output signal from the expected value. This information is reentered as quickly as possible. The parameters of the circuit are automatically varied in order to align again the two signals according to the desired frequency ratio.
Electronic devices used in different applications (for instance in automotive, aeronautics, etc.) are subject, during functioning, to particularly high noise levels that disturb analog circuits such as the PLL. These disturbances often cause loss of the locked condition, to which the PLL reacts in long response times. This reaction depends on the architecture and the parameters of the loop, i.e., characteristics of the filter. A block diagram of a typical analog phase-locked loop is depicted in FIG. 1 (VCO stands for Voltage Controlled Oscillator).
The presence of an auxiliary circuit for verifying the locked condition of the PLL becomes indispensable in the above mentioned situations. This is because the system must have the possibility of reacting properly whenever the noise reaches a level such that the execution of the functions required from the integrated device may be in jeopardy, or, even worse, an incorrect functioning may occur at the system level compromising safety. For instance, in the automotive field safety is very important in airbag electronic controls and in the ABS.
An important problem to be solved in defining the architecture of such a monitoring circuit is to strike the best compromise between the requirement of adequate sensitivity in detecting the locked condition or the loss of it, and that of filtering out momentary loss of locking that are not significant for a correct functioning of the system.
In general the following criteria are defined:
Detection of a Locked Condition:
The system is defined as locked when such a condition remains stable in time. Overshoots in reaching a phase-locked state could be misinterpreted as if the locked condition had been reached. It may just be a temporary coincidence that the successive detection may not be confirmed causing an anomalous functioning of the system. For example, exceptions and/or interrupts may be generated, emergency and/or resume routines may start, and the like.
Detection of a Loss of Locking:
Desirably, the system should filter events having a loss of locking with a very short duration, and signal only persistent losses of locking. This later allows emergency and resume routines to be started only when they are really necessary. This avoids causing false functioning exceptions at any minimal noise injection.
The above mentioned conditions are particularly relevant when the circuit for monitoring the locked condition is digital, wherein the stochastic effects relative to the conditions that occur at the instant in which the decision is taken (PLL locked or not) have a fundamental role. A digital circuit is intrinsically more robust than an equivalent analog circuit, and therefore more suitable in case of particularly noisy environments.
Referring to the basic diagram of FIG. 1, a typical digital approach contemplates implementation of two counters respectively driven by the two signals to be compared in frequency, that is, the reference signal (input signal of the PLL) and the output signal (properly divided) that is fed-back to the input to the analog comparator circuit of the PLL (Phase Comparator). When one of the two counters reaches the end count value, the instantaneous contents of the two counters are compared, producing the result. If the two counters are aligned, the PLL is assumed to be locked, and vice-versa. Any difference between the compared values of the two counters is considered to verify an absence of a locking condition. There are drawbacks that are often unacceptable for applications particularly exposed to noise, and where safety has a fundamental role.
False Detection of a Locked Condition:
When the circuit is turned on, during an initial transient period, the PLL generates an output signal that approximates as much as possible the steady state value, defined by the ratio between the reference frequency and the set multiplication factor. The greater the speed of the circuit, the larger the overshoots in frequency about the expected value.
As depicted in FIG. 2, the two counters, depending on the end count value carry out substantially an average on the effective value of the frequency. While the reference signal is stable (by definition), the signal generated by the PLL, suitably scaled, oscillates in frequency with a mean value detected from the associated counter. As a consequence, during the transient turn on phase, it may happen that the two counters are aligned, notwithstanding that the output signal of the PLL is unstable and should not be used by the application as a signal for timing and synchronizing all logic operations.
False Detection of a Loss of Locking:
Starting from a condition of locking, a perturbation may lead temporarily to a condition in which the output of the PLL differs (in frequency) from the expected value. The feed-back loop reacts immediately trying to compensate the variation, generating a slight overshoot. This temporary situation is in general filtered by the relative long length of the counting, as depicted in FIG. 3a. The probability that the injection of a disturbance takes place when the counters are almost at the end of a count is smaller as the period of counting is longer. Unfortunately, such a probability is never null. This implies that even a small disturbance, if injected at the moment when the two counters are almost terminating the counting, could make the filtering action of the counters ineffective. This causes the generation of a loss of a locking signal, as depicted in FIG. 3b. 
Critical Choice of the End Count Signal:
The choice of the end count signal for the two counters determines the sensitivity of the detection circuit. If, on one hand, a short counting period ensures a most immediate reaction of the system to a perturbation of the equilibrium condition (locking). On the other hand, it makes the system excessively sensitive to occasional short lived events that could be neglected. Often, in some applications, the two opposite requirements have both a vital importance for the functionality of the whole system. For example, there is the need of reacting promptly to an eventual failure of the device that generates the frequency reference signal by triggering emergency routines. On the contrary, a momentary injection of high level noise may cause a temporary condition of a loss of locking that a system may be perfectly able to operate without triggering dedicated procedures for managing the event.
An object of the present invention is to overcome the above mentioned critical points and drawbacks of the known circuits for monitoring a phase-locked condition, and to provide an improved system for generating a clock signal based on a frequency stable reference signal.
The phase lock detecting circuit of the invention is based on the use of a resettable memory with a capacity (in terms of number of bits) sufficient to store a certain number of signals or logic values. These signals or logic values result from a sequence of as many successive comparisons of the values contained in the two counters of a common digital circuit for phase lock detection of the prior art, and of logic circuits for generating a certain logic signal confirming a locked condition upon the occurrence of an uninterrupted sequence of a certain number of logic signals all confirming a locked condition and a different logic signal. This is indicative of a loss of a lock condition upon the occurrence of an uninterrupted sequence of a certain number of logic signals having different values at the input of the resettable memory.
In other words, the circuit exploits a resettable memory suitable to register, at each end count of a common digital circuit for the detection of a phase lock condition of the prior art, the result of the comparison between the content of the two counters of the phase lock detection circuit. A confirmation signal of the detection of a phase lock condition or of a loss of a lock condition is provided to the system only after the memory has stored an uninterrupted series of identical signals either of locking or of loss of locking. The number of which may be pre-defined in the design stage or programmed by the user, even in a dynamically variable fashion depending on one or more operation parameters of the system, which are purposely monitored.
The depth of the resettable memory (that is, the number of successive comparisons that are required for confirming either a locking condition or a loss of a locking condition) may be set by the user himself. Moreover, the sensitivity of detection of a locked condition and of a loss of locking may be set even with different depths independently from one another, depending on the application, and the settings may even be dynamically modified to adapt to changing operating conditions.
The invention is more precisely defined in the annexed claims.